EN25QH256 Datasheet, PDF (47/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Figure 23. Sector Erase Instruction Sequence Diagram
Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address
mode, the address cycles will be increased.
Block Erase (BE) (D8h)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside the chosen block. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write
Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Block Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the in-
struction code, and three or four address bytes (depending on mode state) on Serial Data Input (DI).
Any address inside the Block (see Table 2) is a valid address for the Block Erase (BE) instruction. Chip
Select (CS#) must be driven Low for the entire duration of the sequence.
The default mode is 3-byte address, to access higher address (4-byte address) which requires to enter
the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)
Mode section.
The instruction sequence is shown in Figure 24. Chip Select (CS#) must be driven High after the eighth
bit of the last address byte has been latched in, otherwise the Block Erase (BE) instruction is not
executed. As soon as Chip Select (CS#) is driven High, the self-timed Block Erase cycle (whose du-
ration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a block which is protected by the Block Protect (BP3, BP2,
BP1, BP0) bits (see Table 3) is not executed.
The instruction sequence is shown in Figure 24.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
47
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com