EN25QH256 Datasheet, PDF(41/74 Page) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

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EN25QH256 Datasheet, PDF (41/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

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EN25QH256

Quad Input / Output FAST_READ (EBh)

The Quad Input/Output FAST_READ (EBh) instruction is similar to the Dual I/O Fast Read (BBh)

instruction except that address (3-byte or 4-byte, depending on mode state) and data bits are input and

output through four pins, DQ0, DQ1, DQ2 and DQ3 and six dummy clocks are required prior to the data

output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code

execution (XIP) directly from the Quad SPI.

The Quad Input/Output FAST_READ (EBh) instruction enable quad throughput of Serial Flash in read

mode. In SPI mode, the QE bit needs to be assigned through WRSR to set to â1â before sending the

SPI instruction Quad Input/Output FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI),

this QE bit becomes no affection since WP# and HOLD# function will be disabled by EQPI mode and

Quad Input/Output FAST_READ (EBh) will be always available in EQPI mode.

The address is latching on rising edge of CLK, and data of every four bits (interleave on 4 I/O pins) shift

out on the falling edge of CLK at a maximum frequency FR. The first address can be any location. The

address is automatically increased to the next higher address after each byte data is shifted out, so the

whole memory can be read out at a single Quad Input/Output FAST_READ instruction. The address

counter rolls over to 0 when the highest address has been reached. Once writing Quad Input/Output

FAST_READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous

1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to

enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode

(EN4B) Mode section.

The sequence of issuing Quad Input/Output FAST_READ (EBh) instruction is: CS# goes low ->

sending Quad Input/Output FAST_READ (EBh) instruction -> 24-bit or 32-bit address (depending on

mode state ) interleave on DQ3, DQ2, DQ1 and DQ0 -> 6 dummy cycles -> data out interleave on DQ3,

DQ2, DQ1 and DQ0 -> to end Quad Input/Output FAST_READ (EBh) operation can use CS# to high at

any time during data out, as shown in Figure 20.

The instruction sequence is shown in Figure 20.1 while using the Enable Quad Peripheral Interface

mode (EQPI) (38h) command.

Figure 20. Quad Input / Output Fast Read Instruction Sequence Diagram

Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address

mode, the address cycles will be increased.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2012/01/30

www.eonssi.com

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