EN25QH256 Datasheet, PDF (38/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Figure 17.1 Fast Read Instruction Sequence under EQPI Mode
Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address
mode, the address cycles will be increased.
Dual Output Fast Read (3Bh)
The Dual Output Fast Read (3Bh) is similar to the standard Fast Read (0Bh) instruction except that
data is output on two pins, DQ₀ and DQ₁, instead of just DQ₀. This allows data to be transferred from
the EN25QH256 at twice the rate of standard SPI devices. The Dual Output Fast Read instruction is
ideal for quickly downloading code from to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
Similar to the Fast Read instruction, the Dual Output Fast Read instruction can operation at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy clocks after the 3-byte or 4-byte address (depending on mode state) as shown in Figure 18.
The dummy clocks allow the device’s internal circuits additional time for setting up the initial address.
The input data during the dummy clock is “don’t care”. However, the DI pin should be high-impedance
prior to the falling edge of the first data out clock.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to
enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode
(EN4B) Mode section.
This Data Sheet may be revised by subsequent versions
38
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com