EN25QH256 Datasheet, PDF (35/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Exit High Bank Latch mode (EXHBL) (98h)
The Exit High Bank Latch Mode (EXHBL) instruction is executed to exit the High Bank Latch mode and
then return to the default state: the first byte addresses was accessed at memory area of lower bank
(smaller than 128M) while execute the read / program / erase command. After sending out the EXHBL
instruction, the bit 7 (HBL bit) of Information register will be cleared to be ”0” to indicate the exit of the
High Bank Latch mode. Once the exit the High Bank Latch mode is enable, if executed the read /
program / erase command then the first byte addresses will be accessed at memory area of lower bank
(smaller than 128M).
The sequence of issuing EXHBL instruction is: CS# goes low -> sending EXHBL instruction to Exit High
Bank Latch mode (automatically clear the HBL bit to be “0”) -> CS# goes high, as shown in Figure 15.
The instruction sequence is shown in Figure 15.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Figure 15. Exit High Bank Latch mode Instruction Sequence Diagram
Figure 15.1 Enter / Exit High Bank Latch mode Instruction Sequence under EQPI Mode
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com