EN25QH256 Datasheet, PDF (42/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Figure 20.1. Quad Input / Output Fast Read Instruction Sequence under EQPI Mode
Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address
mode, the address cycles will be increased.
Another sequence of issuing Quad Input/Output FAST_READ (EBh) instruction especially useful in
random access is : CS# goes low -> sending Quad Input/Output FAST_READ (EBh) instruction -> 24-
bit address interleave on DQ₃, DQ₂, DQ₁ and DQ₀ -> performance enhance toggling bit P[7:0] -> 4
dummy cycles -> data out interleave on DQ₃, DQ₂, DQ₁ and DQ₀ till CS# goes high -> CS# goes low
(reduce Quad Input/Output FAST_READ (EBh) instruction) -> 24-bit or 32-bit random access address
(depending on mode state), as shown in Figure 21.
In the performance – enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0] = A5h, 5Ah,
F0h or 0Fh can make this mode continue and reduce the next Quad Input/Output FAST_READ (EBh)
instruction. Once P[7:4] is no longer toggling with P[3:0] ; likewise P[7:0] = FFh, 00h, AAh or 55h. And
afterwards CS# is raised, the system then will escape from performance enhance mode and return to
normal operation.
While Program/ Erase/ Write Status Register is in progress, Quad Input/Output FAST_READ (EBh)
instruction is rejected without impact on the Program/ Erase/ Write Status Register current cycle.
The instruction sequence is shown in Figure 21.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
This Data Sheet may be revised by subsequent versions
42
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com