EN25QH256 Datasheet, PDF (18/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25QH256 provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction
completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3 BP2 BP1 BP0
Bit Bit Bit Bit
Protect Areas
Addresses
Density(KB) Portion
00
0
0
None
None
None
None
00
0
1
Block 511
1FF0000h-1FFFFFFh 64KB
Upper 1/512
00
1
0
Block 510 to 511 1FE0000h-1FFFFFFh 128KB
Upper 2/512
00
1
1
Block 508 to 511 1FC0000h-1FFFFFFh 256KB
Upper 4/512
01
0
0
Block 504 to 511 1F80000h-1FFFFFFh 512KB
Upper 8/512
01
0
1
Block 496 to 511 1F00000h-1FFFFFFh 1024KB
Upper 16/512
01
1
0
Block 480 to 511 1E00000h-1FFFFFFh 2048KB
Upper 32/512
01
1
1
All
0000000h-1FFFFFFh 32768KB All
10
0
0
None
None
None
None
10
0
1
Block 0
0000000h-000FFFFh 64KB
Lower 1/512
10
1
0
Block 0 to 1
0000000h-001FFFFh 128KB
Lower 2/512
10
1
1
Block 0 to 3
0000000h-003FFFFh 256KB
Lower 4/512
11
0
0
Block 0 to 7
0000000h-007FFFFh 512KB
Lower 8/512
11
0
1
Block 0 to 15
0000000h-00FFFFFh 1024KB
Lower 16/512
11
1
0
Block 0 to 31
0000000h-01FFFFFh 2048KB
Lower 32/512
11
1
1
All
0000000h-1FFFFFFh 32768KB All
This Data Sheet may be revised by subsequent versions
18
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com