EN25QH256 Datasheet, PDF (30/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
The status and control bits of the Secured Register are as follows:
Reserved bit. Information register bit locations 0, 3 and 4 are reserved for future use. Current devices
will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the
Suspend Status Register. Doing this will ensure compatibility with future devices.
OTP_LOCK bit. The OTP_LOCK bit, user can read/program/erase OTP sector as normal sector while
OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR command, the
OTP sector is protected from program and erase operation. The OTP_LOCK bit can only be
programmed once.
4 BYTE Indicator bit. By writing EN4B instruction, the 4 BYTE bit may be set to “1” to access the
address length of 32-bit for higher density (large than 128Mb) memory area. The default state is “0”,
which means the mode of 24-bit address. The 4 BYTE bit may be clear by power off or writing EX4B
instruction to reset the state to be “0”
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This
bit will also be set when the user attempts to program a protected main memory region or a locked OTP
region. This bit can indicate whether one or more of program operations fail, and can be reset by
Program (PP) or Erase (SE, BE or CE) instructions.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will
also be set when the user attempts to erase a protected main memory region or a locked OTP region.
This bit can indicate whether one or more of erase operations fail, and can be reset by Program (PP) or
Erase (SE, BE or CE) instructions.
Note : For Program and Erase Flag bits,
1. The flag bits can be reset by power-on or that embedded mode was executed like WRSR, Erase or
Program command.
2. If the system is trying to erase a locked block and then program a locked block. The erase fail or
program fail flag bit will be high due to no successful Program, Erase or WRSE command.
HBL bit. The High Bank Latch (HBL) bit indicates the status of the internal High Bank Latch. By writing
ENHB instruction, the HBL bit may be set to “1” to access the memory area of higher bank (larger than
128M). The default state is “0”, which mean if execute read / program / erase command, then the first
byte addresses will be accessed at the memory area of lower density (smaller than 128M). The HBL bit
may be clear by power off or writing EXHBL instruction to reset the state to be “0”
Write Status Register (WRSR) (01h)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write
Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by
the instruction code and the data byte on Serial Data Input (DI).
The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no
effect on S1 and S0 of the Status Register. Chip Select (CS#) must be driven High after the eighth bit of
the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed.
As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose
duration is t_W) is initiated. While the Write Status Register cycle is in progress, the Status Register may
still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect
(BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table 3. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register
Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware
Protected Mode (HPM) is entered.
This Data Sheet may be revised by subsequent versions
30
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com