EN25QH256 Datasheet, PDF (28/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
The Chip Erase (CE) instruction is executed if, and only if, all Block Protect (BP3, BP2, BP1, BP0) bits
are 0.
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ
(EBh) will be always available in EQPI mode.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow
the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set
to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register
(SRP, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is
no longer accepted for execution.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Read Information Register (RDIFR) (2Bh)
The Read Information Register (RDIFR) instruction is for reading the value of Information Register. The
Read Information Register can be read at any time (even in program/erase/write status register
condition) and continuously, as shown in Figure 10.
The sequence of issuing RDIFR instruction is: CS# goes low -> sending RDIFR instruction ->
Information Register data out on DO -> CS# goes high.
The instruction sequence is shown in Figure 10.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Figure 10. Read Information register Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
28
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com