EN25QH256 Datasheet, PDF (34/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Enter High Bank Latch mode (ENHBL) (67h)
The High Bank Latch mode (ENHBL) instruction enables the first byte addresses was accessed at the
memory area of higher bank (larger than 128Mb) while execute the read / program / erase command,
that means the address 24-bit was asserted high after entering this mode. In other words, for read /
program / erase command the Host system can also access the addresses from 1000000h to 1FFFFFF
even if without inputting 4 byte address. The device default is in the memory area of lower bank
(smaller than 128M); after sending out the ENHBL instruction, the bit 7 (HBL bit) of Information register
will be automatically set to “1” to indicate the High Bank Latch has been enabled. Once the High Bank
Latch mode is enable, if execute read / program / erase command, then the first byte addresses will be
accessed at memory area of the higher bank (larger than 128Mb) instead of the default the memory
area lower bank (smaller than 128M).
There are some methods that can exit the High Bank Latch mode: power-off, or by writing Reset Quad
I/O (RSTQIO), Enter 4-byte mode (EN4B) and Exit High Bank Latch mode (EXHBL) instructions.
The sequence of issuing ENHBL instruction is: CS# goes low -> sending ENHBL instruction to enter
High Bank Latch mode (automatically set HBL bit as “1”) -> CS# goes high, as shown in Figure 14.
The instruction sequence is shown in Figure 15.1 while using the Enable Quad Peripheral Interface
mode (EQPI) (38h) command.
Figure 14. Enter High Bank Latch mode Instruction Sequence Diagram
This Data Sheet may be revised by subsequent versions
34
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com