EN25QH256 Datasheet, PDF (17/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
Status Register and Information Register
The Status Register and Information Register contain a number of status and control bits that can be
read or set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define
the size of the area to be software protected against Program and Erase instructions.
QE bit. The Quad Enable (QE) bit, non-volatile bit, enable bit only for Quad Input/Output FAST_READ
(EBh) in SPI command. When it is “0” (factory default), it disables Quad Input/Output FAST_READ
(EBh) in SPI command and WP#, HOLD# are enabled. While QE is “1”, it enables Quad Input/Output
FAST_READ (EBh) in SPI command and WP#, HOLD# are disabled. In other words, in SPI mode, the
QE bit needs to be assigned through WRSR to enable or disable SPI command Quad Input/Output
FAST_READ (EBh). If the system goes into Full Quad I/O (EQPI), this QE bit becomes no affection
since WP# and HOLD# function will be disabled by EQPI mode and Quad Input/Output FAST_READ
(EBh) will be always available in EQPI mode.
SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit operates in conjunction with the Write
Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the
device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status
Register (SRP, BP3, BP2, BP1, BP0) become read-only bits.
In OTP mode, this bit serves as OTP_LOCK bit, user can read/program/erase OTP sector as normal
sector while OTP_LOCK bit value is equal 0, after OTP_LOCK bit is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can only
be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
4 BYTE Indicator bit. By writing EN4B instruction, the 4 BYTE bit may be set to “1” to access the
address length of 32-bit for higher density (larger than 128Mb) memory area. The default state is “0”,
which means the mode of 24-bit address. The 4 BYTE bit may be clear by power off or writing EX4B
instruction to reset the state to be “0”
Program Fail Flag bit. While a program failure happened, the Program Fail Flag bit would be set. This
bit will also be set when the user attempts to program a protected main memory region or a locked OTP
region. This bit can indicate whether one or more of program operations fail, and can be reset by
Program (PP) or Erase (SE, BE or CE) instructions.
Erase Fail Flag bit. While an erase failure happened, the Erase Fail Flag bit would be set. This bit will
also be set when the user attempts to erase a protected main memory region or a locked OTP region.
This bit can indicate whether one or more of erase operations fail, and can be reset by Program (PP) or
Erase (SE, BE or CE) instructions.
Note : For Program and Erase Flag bits,
1. The flag bits can be reset by power-on or that embedded mode was executed like WRSR, Erase or
Program command.
2. If the system is trying to erase a locked block and then program a locked block. The erase fail or
program fail flag bit will be high due to no successful Program, Erase or WRSE command.
This Data Sheet may be revised by subsequent versions
17
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com