EN25QH256 Datasheet, PDF (39/74 Pages) Eon Silicon Solution Inc. – 256 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25QH256
Figure 18. Dual Output Fast Read Instruction Sequence Diagram
Note: Please note the above address cycles are base on 3-byte address mode, for 4-byte address
mode, the address cycles will be increased.
Dual Input / Output FAST_READ (BBh)
The Dual I/O Fast Read (BBh) instruction allows for improved random access while maintaining two IO
pins, DQ₀ and DQ₁. It is similar to the Dual Output Fast Read (3Bh) instruction but with the capability to
input the Address bits (3-byte or 4-byte, depending on mode state) two bits per clock. This reduced
instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
The Dual I/O Fast Read instruction enable double throughput of Serial Flash in read mode. The
address is latched on rising edge of CLK, and data of every two bits (interleave 2 I/O pins) shift out on
the falling edge of CLK at a maximum frequency. The first address can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single Dual I/O Fast Read instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing Dual I/O Fast Read instruction, the following
address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in Figure 19.
The default read mode is 3-byte address, to access higher address (4-byte address) which requires to
enter the 4-byte address read mode. To enter the 4-byte mode, please refer to the enter 4-byte mode
(EN4B) Mode section.
This Data Sheet may be revised by subsequent versions
39
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com