BCM4390DKWBGT Datasheet, PDF (72/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
Sequencing of Reset and Regulator Control Signals
Control Signal Timing Diagrams
Figure 13: WLAN = ON, APPS CPU = ON
32.678 kHz
Sleep Clock
VBAT*
90% of VH
VDDIO
WL_REG_ON
~ 2 Sleep cycles
APPS_REG_ON
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high
before VBAT is high.
Figure 14: WLAN = OFF, APPS CPU = OFF
32.678 kHz
Sleep Clock
VBAT*
VDDIO
WL_REG_ON
APPS_REG_ON
*Notes:
1. VBATshouldnotrise 10%–90%faster than40microseconds.
2. VBATshouldbeupbeforeorat thesametimeasVDDIO. VDDIOshouldNOTbepresentfirst orbeheldhighbeforeVBATishigh.
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 71
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