BCM4390DKWBGT Datasheet, PDF (71/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
Power-Up Sequence and Timing
Section 14: Power-Up Sequence and Timing
Sequencing of Reset and Regulator Control Signals
The BCM4390 has two signals that allow the host to control power consumption by enabling or disabling the
APPS CPU, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are
provided to indicate proper sequencing of the signals for various operational states (see Figure 13 and
Figure 14 on page 71, and Figure 15 and Figure 16 on page 72). The timing values indicated are minimum
required values; longer delays are also acceptable.
Description of Control Signals
• WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the APPS_REG_ON
input to control the internal BCM4390 regulators. When this pin is high, the regulators are enabled and
the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the
APPS_REG_ON and WL_REG_ON pins are low, the regulators are disabled.
• APPS_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4390
regulators. If both the APPS_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When
this pin is low and WL_REG_ON is high, the APPS CPU section is in reset.
Note: For both the WL_REG_ON and APPS_REG_ON pins, there should be at least a 10 ms time delay
between consecutive toggles (where both signals have been driven low). This is to allow time for the
CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current
on the order of 36 mA during the next PMU cold start.
Note: The BCM4390 has an internal power-on reset (POR) circuit. The device will be held in reset for
a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold.
Note: VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at
the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
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February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 70
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