BCM4390DKWBGT Datasheet, PDF (27/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
General Purpose Input and Output
The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned
with the MSB of the I²S, per the I²S specification. The MSB of each data word is transmitted one-bit clock cycle
after the I²S WS transition, synchronous with the falling edge of the bit clock.
Left-channel data is transmitted when I²S WS is low: right-channel data is transmitted when I²S WS is high.
Data bits sent by the BCM4390 are synchronized with the falling edge of I2S_SCLK and should be sampled by
the receiver on the rising edge of I2S_SCK.
In master mode, the clock rate is: 48 KHz x 32 bits per frame = 1.536 MHz.
The master clock is generated from the input reference clock using an N/M clock divider.
In the slave mode, any clock rate up to 3.072 MHz is supported.
General Purpose Input and Output
The BCM4390 has 24 general purpose IO (GPIO) pins that can be configured as input or output. Each IO can be
configured to have internal pull-up or pull-down resistors. At power-on reset all IOs are configured as input with
no pull. Software can configure the IOs appropriately. In power-down modes, the IOs are configured as high-Z
with no pull.
GPIOs are grouped into two banks of twelve GPIOs:
• Bank A GPIOs have alternate functions (seeTable 4: “GPIO Port A Alternate Functions,” on page 23).
• Bank B GPIOs are dedicated GPIOs, except during test (see Table 7).
GPIO
GPIO_B0
GPIO_B1
GPIO_B2
GPIO_B3
GPIO_B4
GPIO_B5
GPIO_B6
GPIO_B7
GPIO_B8
GPIO_B9
GPIO_B10
GPIO_B11
Test Function
–
–
WL_JTAG_TCK
WL_JTAG_TMS
WL_JTAG_TDI
WL_JTAG_TDO
WL_JTAG_TDO
–
–
–
–
–
Table 7: Bank B GPIO Test Functions
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 26
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