BCM4390DKWBGT Datasheet, PDF (17/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
Power-Up/Power-Down/Reset Circuits
Power-Up/Power-Down/Reset Circuits
The BCM4390 has two signals (see Table 1) that enable or disable the application CPU and WLAN subsystems
and the internal regulator blocks, allowing external system circuitry to control power consumption. For timing
diagrams of these signals and the required power-up sequences, see Section 14: “Power-Up Sequence and
Timing,” on page 70.
Table 1: Power-Up/Power-Down/Reset Control Signals
Signal
Description
WL_REG_ON
This signal is used by the PMU (with APPS_REG_ON) to power up the WLAN section. It is also
OR-gated with the APPS_REG_ON input to control the internal BCM4390 regulators. When
this pin is high, the regulators are enabled and the WLAN section is out of reset. When this
pin is low, the WLAN section is in reset. If APPS_REG_ON and WL_REG_ON are both low, the
regulators are disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by
default. It can be disabled through programming.
APPS_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down
the internal BCM4390 regulators. If APPS_REG_ON and WL_REG_ON are low, the regulators
will be disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default.
It can be disabled through programming.
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 16
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