BCM4390DKWBGT Datasheet, PDF (48/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
Signal Descriptions
Bump# NET_NAME
276 VSSC_276
277 VSSC_277
278 VSSC_278
279 VSSC_279
280 VSSC_280
281 VSSC_281
282 VSSC_282
283 VSSC_283
284 VSSC_284
285 VSSC_285
286 VSSC_286
Table 8: 286-Bump WLCSP Coordinates (Cont.)
Package Bump Side View
(0,0 center of die)
X
Y
499.998
699.996
699.996
699.996
660.603
900.003
1090.002
1100.001
1229.997
1229.997
1290.000
–6.651
–806.652
–606.654
–6.651
–1457.550
68.346
–211.653
668.349
508.347
308.349
–211.653
Package Top Side View
(0,0 center of die)
X
Y
–499.998
–699.996
–699.996
–699.996
–660.603
–900.003
–1090.002
–1100.001
–1229.997
–1229.997
–1290.000
–6.651
–806.652
–606.654
–6.651
–1457.550
68.346
–211.653
668.349
508.347
308.349
–211.653
Signal Descriptions
The signal name, type, and description of each pin in the BCM4390 are listed in Table 9. The symbol listed in
the Type column indicates the pin direction (I/O = bidirectional, I = input, O = output) and the internal pull-up/
pull-down characteristics, if any (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor).
Signal Name
APPS_1P2_AVDD
APPS_AC_GND
APPS_AVDD
APPS_AVSS
APPS_WAKE
APPS_I2S_CLK
APPS_I2S_DI
APPS_I2S_DO
APPS_I2S_WS
APPS_JTAG_EN
Table 9: WLCSP and FCFBGA Pin Descriptions
WLCSP Bump #
90, 96, 98, 99
93
79, 80, 82, 84, 87
89, 95, 97, 100
57
44
43
42
45
54
Type Description
PWR Power supply.
GND Connect to ground to reduce system RF
noise.
PWR APPS CPU domain power supply. Connect to
1.2V
GND Ground. Connect to VSSC for ESD mitigation.
I/O Application CPU subsystem. Device wakes
from sleep signal.
I/O _I²_{S clock. Can be master (output) or slave}
(input)
I/O _I²_{S data input.}
I/O _I²_{S data output.}
I/O _I²_{S word select (WS).}
I/O Application CPU subsystem: JTAG enable.
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 47
BROADCOM CONFIDENTIAL