BCM4390DKWBGT Datasheet, PDF (15/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
Power Management
Power Management
The BCM4390 has been designed with the stringent power consumption requirements of embedded devices
in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell
libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4390 integrated
RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is
leakage current only. The BCM4390 also includes an advanced WLAN power management unit (PMU)
sequencer. The PMU sequencer provides significant power savings by putting the BCM4390 into various power
management states appropriate to the current environment and activities that are being performed. The
power management unit enables and disables internal regulators, switches, and other blocks based on a
computation of the required resources and a table that describes the relationship between resources and the
time needed to enable and disable them. Power up sequences are fully programmable. Configurable, free-
running counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off
individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the
current mode. Slower clock speeds are used wherever possible.
The BCM4390 WLAN-specific power states are described as follows:
• Active mode— All WLAN blocks in the BCM4390 are powered up and fully functional with active carrier
sensing and frame transmission and receiving. All required regulators are enabled and put in the most
efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
• Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of
the WLAN portion of the BCM4390 remains powered up in an IDLE state. All main clocks (PLL, crystal
oscillator or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is
available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up
the chip and transition to Active mode. In Doze mode, the primary power consumed by the WLAN core is
due to leakage current.
• Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators
are powered off. Logic states in the digital core are saved and preserved into a retention memory in the
always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU
timers or an external interrupt, logic states in the digital core are restored to their pre-deep-sleep settings
to avoid lengthy HW reinitialization.
• Power-down mode—The BCM4390 is effectively powered off by shutting down all internal regulators. The
chip is brought out of this mode by external logic re-enabling the internal regulators.
The BCM4390 application processor subsystem can be independently powered on or off at the system level in
the power-down mode. In addition it is also possible to keep the application processor in active mode while
the WLAN blocks are in Doze or Deep-Sleep.
PMU Sequencing
The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various
system resources based on a computation of the required resources and a table that describes the relationship
between resources and the time needed to enable and disable them.
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 14
BROADCOM CONFIDENTIAL