BCM4390DKWBGT Datasheet, PDF (30/78 Pages) Cypress Semiconductor – WICED™ Wi-Fi IEEE 802.11 b/g/n SoC with Embedded Application Processor

BCM4390 Advance Data Sheet
JTAG Interfaces
JTAG Interfaces
The BCM4390 applications core and WLAN core have independent support for the IEEE 1149.1 JTAG boundary
scan standard for performing application firmware debugging and device package and PCB assembly testing
during manufacturing.
The applications core JTAG port provides developers with single-step thread-aware and memory inspection
debugging capability using the Broadcom WICED development system.
The WLAN core JTAG interface allows Broadcom to assist customers by using proprietary debug and
characterization test tools during board bring-up. Therefore it is highly recommended to provide access to the
JTAG pins by means of test points or a header on all PCB designs.
Boot Sequence
Figure 7 shows the boot sequence from power-up to firmware download.
Figure 7: Boot Sequence
VBAT*
VDDIO
WL_REG_ON
VDDC
(from internal PMU)
Internal POR
< 950 µs
< 104 ms
< 4 ms
Device requests for reference clock
8 ms
After 8 ms the reference clock is
assumed to be up. Access to PLL
registers is possible.
Chip active interrupt is asserted after the PLL locks
*Notes:
1. VBAT should not rise 10%–90% faster than 40 microseconds.
2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.
BROADCOM ®
February 5, 2014 • 4390-DS103-R
WICED Wi-Fi IEEE 802.11 SoC w/Embedded App Processor
Page 29
BROADCOM CONFIDENTIAL