CMX989 Datasheet, PDF (28/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
Timing Diagrams (continued)
For the following conditions unless otherwise specified:
Xtal Frequency = 4.9152MHz,
V_DD = 3.0V to 5.5V, Tamb = - 40°C to +85°C and V_DD = 2.7V at Tamb = 25°C.
Notes Min. Typ.
µC Parallel Interface Timings (ref. Figure 5)
t_ACSL
t_AH
t_CSH
t_CSHI
t_CSRWL
t_DHR
t_DHW
t_DSW
t_RHCSL
t_RACL
t_RARL
t_RL
t_RX
t_WHCSL
t_WL
Address valid to CSN low time
Address hold time
CSN hold time
CSN high time
CSN to WRN or RDN low time
Read data hold time
Write data hold time
Write data setup time
RDN high to CSN low time (write)
Read access time from CSN low
Read access time from RDN low
RDN low time
RDN high to D0-D7 3-state time
WRN high to CSN low time (read)
WRN low time
0
–
0
–
0
–
12
6
–
0
–
0
–
0
–
15
–
0
–
11
–
–
11
–
–
35
–
–
–
0
–
35
–
Max.
Units
–
ns
–
ns
–
ns
– clock cycles
–
ns
–
ns
–
ns
–
ns
–
ns
30
ns
25
ns
–
ns
10
ns
–
ns
–
ns
Notes:
11. With 30pF max to V_SS on D0 - D7 pins
12. Xtal/Clock cycles at the XTAL/CLOCK pin
© 2001 Consumer Microcircuits Limited
28
D/989/2