CMX989 Datasheet, PDF (16/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
Read Only Register Description
RX DATA BUFFER Register (Hex address $00)
This is a read-only register of the receive data buffer. It should be read in response to an RXF IRQ FLAG
being set to “1”. Bit 7 is the msb. The interval between RXF interrupts varies from approximately 16µs
to 22ms, depending on the position within the internal data processing sequence.
RX COLOUR CODE Register (Hex address $01)
This is a ready-only register of the Colour Code on the Rx (Forward Channel). It is updated every time
the SYNCF IRQ FLAG is set to “1”. Bit 7 is the msb.
STATUS Register (Hex address $02)
This is a read-only register that contains the status of the various functions on the device as described
below:
SYNC
(Bit 7)
This bit is set to “1” if a Forward Channel synchronisation word has been received
successfully. (See SYNC ERRORS and SYNC ERROR LIMIT). This bit is reset to
“0” when the sync word has not been detected for more than 420 bits (i.e. sync lost).
DEC
(Bit 6)
This bit indicates the decode status of the Mobile Data Base Station (MDBS) on the
Forward Channel. This bit is set to “1” when the station fails to decode data
successfully, and is reset to “0” when the station is successful in decoding data.
This bit will only change and be valid if SYNC (Bit 7) is set to “1”.
IDLE
(Bit 5)
This bit indicates the activity of the Mobile Data Base Station (MDBS) on the
Forward Channel. This bit is set to “1” when the station is in an IDLE state, and
reset to “0” when the station is in a BUSY state. This bit will only change and be
valid if SYNC (Bit 7) is set to “1”. The value of this bit is not specified if SYNC (Bit
7) is reset to "0".
The IDLE bit is derived from a majority decision on the most recently received group
of five consecutive busy/idle bits, as in the CDPD specification (Release 1.1, Part
402, Section 4.5, Figure 402-7).
The first block of data received in the Forward Channel will not output any data until
the sync word has been found. Once this has been found, the majority decision of
the most recent group of busy/idle bits will be output in the STATUS register, and
the IDLEF bit will be set to “1” in the IRQ FLAGS register.
The next six groups of busy/idle bits generate IDLE bits as they are received and, so
long as the sync word remains correct, these successive IDLE bits are output as the
groups of busy/idle bits are received.
(Bit 4)
Unused, will be set to “0”.
TXRFEN
(Bit 3)
This bit is set to "1" approximately two bits (104µs) before the dotting sequence
leaves TXOP1 or TXOP2 outputs and is reset to "0" at the end of transmission from
TXOP1 and TXOP2. This signal is also available as a direct output on the TXRFEN
pin, where it can be used to enable an external RF power amplifier stage.
© 2001 Consumer Microcircuits Limited
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D/989/2