CMX989 Datasheet, PDF (24/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
8. The Tx buffer can be kept full and serviced with an interrupt routine. There is no buffer empty
indication and failure to provide data after writing the START bit will cause the device to send
undefined data. Transmission of data does not begin until one complete block has been loaded
into the Tx buffer.
9. The transmission will automatically start within 8 bit-times of the last bit of an idle flag (see the
CDPD specification: Release 1.1, Part 402, Section 5.3.1). Approximately two bit-times (104µs)
before the transmission is present at the TXOP1 and TXOP2 pins, the TXRFEN pin will be set to
"1" and the TXRFEN bit (STATUS register Bit 3) will also be set to "1". The interrupt flag TXRFF
(Bit 3 of the IRQ FLAGS 2 register) will also be set to "1" and an interrupt (IRQN) will be
generated if the mask has previously been enabled (TXRFM, Bit 3 of the IRQ MASK 2 register
set to "1").
10. Completion of the last Reed-Solomon block transmission will cause the TXRFEN pin to be reset
to "0" and the TXRFEN bit (STATUS register Bit 3) will also be reset to "0". The interrupt flag
TXRFF (Bit 3 of the IRQ FLAGS 2 register) will be set to "1" and an interrupt (IRQN) will be
generated if the mask has previously been enabled (TXRFM, Bit 3 of the IRQ MASK 2 register
set to "1"). Finally, the outputs TXOP1 and TXOP2 will go to V_BIAS.
ENABTX (Bit 0 of the TX CONTROL register) should then be reset to "0", if required.
11. DECF (Bit 6 of the IRQ FLAGS register) and DEC (Bit 6 of the STATUS register) should be
monitored to determine whether the M-ES Reverse Channel transmitted data has been decoded
correctly by the MDBS.
© 2001 Consumer Microcircuits Limited
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