CMX989 Datasheet, PDF (23/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
4. If an ERRF interrupt (Bit 2 of the IRQ FLAGS register) and ERR (Bit 2 of the STATUS register)
occur, the host µController will be expected to discard the bytes that it has already read from the
receiver, which are associated with the unfinished frame. It must then wait for the next Frame
flag (RXFRMF) in order to continue. Any unread contents of the RX DATA BUFFER are
automatically discarded and no further RXF interrupts will be generated until the next Frame flag
(RXFRMF) interrupt occurs.
5. As the device can buffer up to 4 Reed-Solomon blocks i.e. 4 x 47 x 6 = 1128 bits = 141 bytes, in
addition to the Reed-Solomon block it is currently decoding, it may be more convenient for the
host µController to use BLKRDYF and BLKRDYM (Bit 7 of the IRQ MASK 2 register and Bit 7 of
the IRQ FLAGS 2 register) as a form of counter, such that after 1, 2, 3, or 4 "Block Ready"
interrupts, the host µController empties the receive buffer in one go. Since, in this case, there is
no way of knowing when the buffer is empty, an external timeout or byte counter is also required.
6. There is no buffer full indication, so if the RX DATA BUFFER register is not sufficiently empty
when the fifth block has been processed, the latest received data (i.e. the fourth block) will be
overwritten by the just completed fifth block.
Transmit
The host µController then processes the frames and decides upon a reply. Gaining access and replying
on the Reverse Channel can be done as follows:
1. Before starting a transmission the COLOURF flag (Bit 3 of the IRQ FLAGS register) should be
checked to have been set to “1” to ensure the correct Colour Code is used on the Reverse
Channel (this could be done whilst also reading the STATUS register during receive).
2. The IDLEF flag (Bit 5 of the IRQ FLAGS register) and the IDLE bit (Bit 5 of the STATUS register)
should be checked to see if the Forward Channel is free. If the IDLE bit is “1” the channel is free,
if it is “0” then there is communication with another system and the host µController will enter the
DEFER state according to the CDPD specification (Release 1.1, Part 402, Sections 5.3.3.1 and
5.3.3.2).
3. With the IDLE bit confirming a free channel, set the desired MOD1 and MOD2 output gains in the
TX MODEM CONTROL register, then write “1” to TXRFM (IRQ MASK 2 register, Bit 3) and write
"1" to ENABTX (TX CONTROL register, Bit 0). This will take the Tx processing circuits out of
powersave, so that blocks of data can then be loaded.
4. Up to 4 Reed-Solomon blocks (i.e. 4 x 47 x 6 = 1128 bits = 141 bytes of data) can be loaded
contiguously on a byte-by-byte basis. Before any further data is loaded, the transmission must
be started. This is done by writing “1” to START (Bit 1 of the TX CONTROL register), to indicate
the start of data, i.e. the dotting sequence, reverse synchronization Colour Code (from the
Forward Channel) and the first frame byte will automatically be sent before the data in the buffer
is despatched.
5. Write the data into the TX DATA BUFFER register a byte at a time, using the IRQN pin and the
handshaking of the TXF flag (Bit 4 of the IRQ FLAGS register). TXF set to "1" indicates that
another byte can be loaded into the TX DATA BUFFER register. When TXF remains at "0", the
buffer is full.
6. At each frame boundary write a “1” to ENDFRM (Bit 2 of the TX CONTROL register).
7. At the end of the transmission sequence, write “1” to ENDSEQ (Bit 3 of the TX CONTROL
register). This will fill up the last Reed-Solomon block with “1”s and send it with the continuity
indicator set to “0” (see the CDPD specification: Release 1.1, Part 402, Section 4.6.4).
© 2001 Consumer Microcircuits Limited
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