CMX989 Datasheet, PDF (15/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
IRQ MASK 2 Register (Hex address $07)
This register is the counterpart to IRQ FLAGS 2 register. Apart from TXRFM and possibly BLKRDYM,
the bits in this register are mainly for test purposes and should be set to all “0s” for normal operation.
BLKRDYM
(Bit 7)
When this bit is set to “1” the BLKRDY interrupt will be gated out to the IRQN pin.
When this bit is set to “0” the BLKRDY interrupt will be inhibited. This bit has no
effect on the contents of the STATUS register.
(Bit 6)
Unused, set to “0”.
RXDEBUG
(Bit 5)
When this bit is “1” the Rx (Forward Channel) will load data every 420 bits, without
detecting a sync word. When this bit is “0” the device operates normally. This bit is
normally used for debugging only, but could be used in conjunction with bit error
rate measurements.
TXWITHNORX
(Bit 4)
When this bit is “1” the Tx (Reverse Channel) will transmit without waiting for the Rx
(Forward Channel) to synchronise as required by the CDPD specification (Release
1.1, Part 402, Section 5.3.1, Figure 402-16). When this bit is “0” the device
operates normally.
TXRFM
(Bit 3)
When this bit is set to “1” the TXRF interrupt will be gated out to the IRQN pin.
When this bit is set to “0” the TXRF interrupt will be inhibited. This bit has no effect
on the contents of the STATUS register.
RXPULSE
(Bit 2)
When the two bits “RX Bit 1” and “RX Bit 0” are set appropriately and this bit has “1”
written to it, an internal test sequence will be clocked into the Reed-Solomon
decoder and the receiver will output the bits as required by the CDPD specification
(Release 1.1, Part 402, Appendix 402-A, Table 402-8).
RX Bit 1, RX Bit 0 These two bits set the internally generated test sequence for the receiver according
(Bits 1 and 0)
to the table below:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Function
Normal operation
Test sequence 0 errors
Test sequence 8 errors
Test sequence 9 errors
© 2001 Consumer Microcircuits Limited
15
D/989/2