CMX989 Datasheet, PDF (20/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
IRQ FLAGS 2 Register (Hex address $05)
Bits 5 and 6 of this register are for test purposes only and their contents should be ignored during normal
operation.
BLKRDYF
(Bit 7)
This is the “Block Ready Flag” and is set to “1” when the receiver decodes the
currently received Reed-Solomon block. It is reset to “0” after a read of the IRQ
FLAGS 2 register. When this bit is set to “1” an interrupt may be generated
depending on the state of the IRQ MASK 2 register.
ENV
(Bit 6)
A circuit monitors the DOC voltage levels, which are an indication of the received
signal amplitude envelope. If the DOC voltages are more than 6% of V_DD apart
(0.3V when V_DD = 5.0V) then this bit will be set to “1”. It is reset to “0” when the
DOC voltages are less than 6% of V_DD apart.
Note: The ENV output will also be triggered when receiving high levels of
noise or other in-band signals.
EOPN
(Bit 5)
A circuit monitors the receive waveform. If the received signal remains close to the
centre of the received data levels (as stored on the DOC capacitors) for more than
approximately 3 bit-times then this bit will be set to “1”. If the input signal level
goes towards either of the DOC capacitor values this bit will be set to “0”.
Note: When a data signal is not being received and the DOC capacitors have
discharged or if there are high levels of noise then the value of the EOPN bit
will be unreliable and so it should be used in conjunction with the ENV bit.
(Bit 4)
Unused, will be set to “0”.
TXRFF
(Bit 3)
This bit is set to “1” when the Tx RF enable bit (TXRFEN) changes state. This bit is
reset to “0” after a “read” of the IRQ FLAGS 2 register. When this bit is set to “1” an
interrupt may be generated depending on the state of the IRQ MASK 2 register.
(Bits 2, 1 and 0) Unused, will be set to “0”.
© 2001 Consumer Microcircuits Limited
20
D/989/2