CMX989 Datasheet, PDF (21/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
1.6 Application Notes
1.6.1 Operation Sequence
Power Up
When the device is first powered up to ensure that it enters zero power mode correctly and initialise it for
TX/RX, the clock has to be enabled for a period of time to serially Clear/Set/Reset the buffers. The
recommended method is as follows:
0. Issue a General Reset command.
1. Reset write registers
Then
10000000 → RX CONTROL
00000000 → RX CONTROL
2. Enable crystal
00010000 → RX CONTROL
3. Enable test mode
00010000 → IRQMASK2
4. Enable Tx
00000001 → TX CONTROL
5. 50ms delay
6. Reset write registers
Then
1000 0000
0000 0000
RX CONTROL
RX CONTROL
In a normal power up sequence step 6 would be missed out and the 50ms delay would also allow the bias
capacitor to be charged up.
Thus the sequence would continue as below:
6. Disable test mode
0000 0000 → IRQMASK2
7. Enable Rx
0001 1000 → RX CONTROL
8. Clear flags
Read
Read
IRQFLAGS
IRQFLAGS2
9. Set the remaining registers as required.
© 2001 Consumer Microcircuits Limited
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