CMX989 Datasheet, PDF (12/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
RX MODEM CONTROL (Hex address $04)
This register is for test purposes only and should be set to all “00001100” for normal operation.
(Bits 7 and 6)
Unused, set to “0”
LEVRES
(Bits 5 and 4)
These two bits set the response time of the Rx signal amplitude and dc offset
measuring circuits according to the table below:
B5 B4
0
0
0
1
1
0
1
1
Setting
Peak Averaging
Peak Detect
Lossy Peak Detect
Hold
Action
Track input signal using bit peak averaging
Track input signal using peak detect
Track input signal using lossy peak detection
Keep current values of amplitude and offset
This setting will be temporarily overridden by the automatic sequencing of an AQLEV command.
AQLEV
(Bit 3)
Whenever the AQLEV bit is set to “0” it initiates an automatic sequence
designed to measure the amplitude and dc offset of the received signal as
rapidly as possible. This sequence involves setting the measurement circuits to
respond quickly at first, then gradually increasing their response time, hence
improving the measurement accuracy, until the ‘normal’ value set by the
LEVRES bits is reached.
Setting this bit to “1” (or changing it from “0” to “1”) has no effect.
AQBC
(Bit 2)
Whenever the AQBC bit is set to “0” it initiates an automatic sequence designed
to achieve bit timing synchronisation with the received signal as quickly as
possible. This involves setting the Phase Locked Loop of the received bit timing
extraction circuits to its widest bandwidth, then gradually reducing the bandwidth
as timing synchronisation is achieved, until it reaches the ‘normal’ value set by
the PLLBW bits.
Setting this bit to “1” (or changing it from “0” to “1”) has not effect.
PLLBW
(Bits 1 and 0)
These two bits set the bandwidth of the Rx clock extraction PLL circuit according
to the table below:
B1 B0
0
0
0
1
1
0
1
1
PLL Bandwidth
Medium
Wide
Narrow
Hold
Suggested Use
Wide tolerance Xtals or long preamble acquisition
Quick acquisition
±20ppm or better Xtals
Signal fades
This setting will be temporarily overridden by the automatic sequencing of an AQBC command.
© 2001 Consumer Microcircuits Limited
12
D/989/2