CMX989 Datasheet, PDF (18/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

CDPD MAC and Data Pump Processor
CMX989
IRQ FLAGS Register (Hex address $03)
This is a read-only register that contains flags to indicate the source of an interrupt, as described below:
SYNCF
(Bit 7)
This bit is set to “1” when the device has decoded the sync word on the Forward
Channel. It also is set to “1” if, after detecting sync, it fails to detect it 420 bits later,
indicating sync has been lost. The state of the sync can be read from the STATUS
register. This bit is reset to “0” after a “read” of the IRQ FLAGS register. When this
bit is set to “1” an interrupt may be generated, depending on the state of the IRQ
MASK register.
DECF
(Bit 6)
This bit is set to “1” when the decode status of the Mobile Data Base Station
(MDBS) in the Forward Channel changes state. The decode state can be read from
the STATUS register. This bit is reset to “0” after a “read” of the IRQ FLAGS
register. When this bit is set to “1” an interrupt may be generated depending on the
state of the IRQ MASK register.
IDLEF
(Bit 5)
This bit is set to “1” when the idle status of the Mobile Data Base Station (MDBS) in
the Forward Channel changes state. The idle state can be read from the STATUS
register. This bit is reset to “0” after a “read” of the IRQ FLAGS register. When this
bit is set to “1” an interrupt may be generated depending on the state of the IRQ
MASK register.
TXF
(Bit 4)
This bit provides handshaking flow control when writing data bytes to the Tx
(Reverse Channel) data buffer. It is set to “1” whenever the buffer is not full and
new data can be loaded in to the TX DATA BUFFER register. It is reset to “0” after
a “write” to the TX DATA BUFFER register. When this bit is set to “1” an interrupt
may be generated depending on the state of the IRQ MASK register. The interval
between TXF interrupts varies from approximately 16µs to 22ms, depending on the
position within the internal data processing sequence.
COLOURF
(Bit 3)
This bit is set to “1” when a colour code is successfully received on the Forward
Channel and placed in the RX COLOUR CODE register. It is reset to “0” after a
read of the IRQ FLAGS register. When this bit is set to “1” an interrupt may be
generated depending on the state of the IRQ MASK register.
ERRF
(Bit 2)
This bit is set to “1” when the ERR status changes. This bit is reset to “0” after a
“read” of the IRQ FLAGS register. When this bit is set to “1” an interrupt may be
generated depending on the state of the IRQ MASK register.
RXF
(Bit 1)
This bit provides handshaking flow control when reading data bytes from the Rx
(Forward Channel) data buffer. It is set to “1” whenever the buffer is not empty and
data is available to be read from the RX DATA BUFFER register. It is reset to “0”
after a “read” of the RX DATA BUFFER register. When this bit is set to “1” an
interrupt may be generated depending on the state of the IRQ MASK register. The
interval between RXF interrupts varies from approximately 16µs to 22ms, depending
on the position within the internal data processing sequence.
RXFRMF
(Bit 0)
This bit is used when reading the receiver data. It is set to “1” when the byte about
to be read from the receiver data buffer is the first byte of a new frame. It is reset to
“0” after a “read” of the IRQ FLAGS register. When this bit is set to “1” an interrupt
may be generated depending on the state of the IRQ MASK register.
© 2001 Consumer Microcircuits Limited
18
D/989/2