CMX989 Datasheet, PDF(11/31 Page) CML Microcircuits – CDPD MAC and Data Pump Processor

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CMX989 Datasheet, PDF (11/31 Pages) CML Microcircuits – CDPD MAC and Data Pump Processor

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CDPD MAC and Data Pump Processor

CMX989

Write Only Register Description

TX DATA BUFFER Register (Hex address $00)

This is a write only register of the Tx Data Buffer. It should be written in response to a TXF IRQ FLAG

being set to â1â. Bit 7 is the msb. The interval between TXF interrupts varies from approximately 16Âµs to

22ms, depending on the position within the internal data processing sequence.

TX COLOUR CODE Register (Hex address $01)

This is a write only register of the Tx Colour Code. This value for the Tx Colour Code is used when the

FORCE COLOUR CODE (Bit 4 of the TX CONTROL register) bit is set to â1â. Bit 7 is the msb.

TX CONTROL Register (Hex address $02)

(Bits 7,6 and 5)

Unused, set to â0â

FORCE COLOUR

CODE

(Bit 4)

When this bit is â1â the Colour Code transmitted in the first block of the Reverse

Channel will be the byte defined in the TX COLOUR CODE register. When this

bit is â0â the Colour Code transmitted will be the Colour Code byte previously

received on the Forward Channel and recorded in the RX COLOUR CODE read-

only register.

ENDSEQ

(Bit 3)

Write a â1â to this bit when the last byte of the last frame in the sequence has

loaded.

ENDFRM

(Bit 2)

At the end of every frame (2-136 bytes) write a â1â to this bit.

START (Bit 1)

Write a â1â to this bit to start the transmission on the Reverse Channel at the

next available slot.

ENABTX

(Bit 0)

When this bit is â1â the Tx (Reverse Channel) is enabled. When this bit is â0â

the Tx (Reverse Channel) is disabled and enters a powersave condition. In this

condition the TXOP1 and TXOP2 outputs are at VBIAS.

RX CONTROL Register (Hex address $03)

RESET

(Bit 7)

Write a â1â followed by a â0â to this bit just after power up to reset all the write

registers.

(Bits 6 and 5)

Unused, set to â0â.

ZERO POWER

(Bit 4)

When this bit is set to â0â the whole device is disabled and set to minimum

power including the crystal oscillator. Allow 20ms for the crystal oscillator to

stabilise when coming out of this zero-power state.

ENABRX

(Bit 3)

When this bit is â1â the Rx (Forward Channel) is enabled. When this bit is â0â

the Rx (Forward Channel) is disabled and enters a powersave condition.

SYNC ERROR LIMIT

(Bits 2, 1 and 0)

This 3-bit number specifies the greatest number of bits that can be in error in the

synchronisation word. Bit 2 is the msb. If the synchronisation word is

recognised with less than or equal to this number of errors, the SYNCF bit is set

to â1â and the actual number of errors is loaded into SYNC ERRORS (Bits 2, 1

and 0 of the RX ERROR DATA register). The RXDATA in that block is then

processed.

D/989/2

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