CS42324 Datasheet, PDF (62/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
6.20.3 DAC1 Auto Mute Left Interrupt Status (DAC1_AMUTEL)
This bit is read only. When set, indicates that DAC1 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam-
ples of zeroes or ones on the left channel of SDIN1, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC1_AMUTELM bit is cleared.
6.20.4 DAC1 Auto Mute Right Interrupt Status (DAC1_AMUTEL)
This bit is read only. When set, indicates that DAC1 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN1, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC1_AMUTERM bit is cleared.
6.20.5 Serial Port 2 Clock Error Interrupt Status (SP2_CLKERR)
This bit is read only. When set, indicates that Serial Port 2 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK2, SCLK2, an
MCLKx/LRCK2 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP2_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if SP2_CLKERRM bit is cleared.
6.20.6 Serial Port 1 Clock Error Interrupt Status (SP1_CLKERR)
This bit is read only. When set, indicates that Serial Port 1 has had a clock error since the last read of this
register. Conditions which cause a clock error in the serial port, such as loss of LRCK1, SCLK1, an
MCLKx/LRCK1 ratio change, or speed mode change, will cause this bit to be set. This interrupt bit is an
edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the SP1_CLKERR[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if SP1_CLKERRM bit is cleared.
6.20.7 ADC Positive Overflow Interrupt Bit (ADC_OVFLP)
This bit is read only. When set, indicates that a positive over-range condition occurred anywhere in the
CS42324 ADC signal path and has ADC data has been clipped to positive full scale since the last read of
this register. This interrupt bit is an edge-triggered event and will be cleared following a read of this reg-
ister.
The INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Address 16h)” on
page 59 and the status of this bit if ADC_OVFLPM bit is cleared. To determine the current overflow state
of the ADC use the OVFL pin.
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DS721A6