CS42324 Datasheet, PDF (61/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
6.19.7 ADC Positive Overflow Mask (ADC_OVFLPM)
This bit serves as a mask for the ADC positive overflow interrupt source. If this bit is cleared, the
ADC_OVFLP interrupt is unmasked, meaning that if the ADC_OVFLP conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Ad-
dress 16h)” register on page 59. If the ADC_OVFLPM bit is set, the ADC_OVFLP condition is masked,
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
6.19.8 ADC Negative Overflow Mask (ADC_OVFLNM)
This bit serves as a mask for the ADC negative overflow interrupt source. If this bit is cleared, the
ADC_OVFLN interrupt is unmasked, meaning that if the ADC_OVFLN conditions are met in the interrupt
status register, the INT pin will go active according to the ADC_OVFLx[1:0] bits in the “Interrupt Mode (Ad-
dress 16h)” register on page 59. If the ADC_OVFLNM bit is set, the ADC_OVFLN condition is masked,
meaning that its occurrence will not affect the INT pin. However, the OVFL pin will continue to reflect the
overflow state of the ADC.
6.20 Interrupt Status (Address 18h) (Read Only)
7
DAC2_
AMUTEL
6
DAC2_
AMUTER
5
DAC1_
AMUTEL
4
DAC1_
AMUTER
3
SP2_
CLKERR
2
SP1_
CLKERR
1
ADC_
OVFLP
0
ADC_
OVFLN
This register defaults to 00h and is read only. If the INT pin is active, reading this register clears the interrupt
condition.
Bit Settings
0
1
Bit in Interrupt Register
Interrupt has not occurred since the last read of this register.
Interrupt has occurred since the last read of this register.
6.20.1 DAC2 Auto Mute Left Interrupt Status (DAC2_AMUTEL)
This bit is read only. When set, indicates that DAC2 left channel has had an auto-mute condition since the
last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive sam-
ples of zeroes or ones on the left channel of SDIN2, will cause this bit to be set. This interrupt status bit
is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC2_AMUTELM bit is cleared.
6.20.2 DAC2 Auto Mute Right Interrupt Status (DAC2_AMUTER)
This bit is read only. When set, indicates that DAC2 right channel has had an auto-mute condition since
the last read of this register. Conditions which cause an auto-mute, such as receiving 4096 consecutive
samples of zeroes or ones on the right channel of SDIN2, will cause this bit to be set. This interrupt status
bit is an edge-triggered event and will be cleared following a read of this register.
The INT pin will go active according to the DAC_AMUTE[1:0] bits in the “Interrupt Mode (Address 16h)”
on page 59 and the status of this bit if DAC2_AMUTERM bit is cleared.
DS721A6
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