CS42324 Datasheet, PDF (32/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

4.2.5
CS42324
Digital Interface Formats
Each converter (ADC, DAC1, and DAC2) has independent selection for serial formats (I²S, Left-Justified,
etc.). Data is clocked out of the ADC or into the DAC on the rising edge of SCLK. Figures 13-17 illustrate
the general structure of each format. Refer to “Switching Characteristics - Serial Audio” on page 22 or
“Switching Characteristics - Serial Audio (Cont.)” on page 23 for exact timing relationship between clocks
and data. For a complete overview of Serial Audio Interface Formats, please reference Application Note
AN282.
DIF (Pin 5) Setting
LO
HI
Left-Justified Interface
I²S Interface
Selection
Table 8. Hardware Mode Interface Format Control
LRCKx
SCLKx
SDIN1/2
SDOUT
MSB
Left Channel
Right Channel
LSB
MSB
AOUTxA
AINxA
AOUTxB
AINxB
Figure 13. Left-Justified up to 24-Bit Data
LSB
MSB
LRCKx
Left Channel
Right Channel
SCLKx
SDIN1/2
SDOUT
MSB
AOUTxA
AINxA
LSB
MSB
AOUTxB
AINxB
LSB
Figure 14. I²S up to 24-Bit Data
MSB
LRCKx
SCLKx
SDIN1/2
SDOUT
Left C hannel
Right Channel
MSB
AOUTxA
AINxA
LSB
MSB
AOUTxB
AINxB
LSB
Figure 15. Right-Justified 16-Bit Data, Right-Justified 24-Bit Data
4.2.6
Synchronization of Multiple Devices
In systems where multiple ADCs and DACs are required, care must be taken to achieve simultaneous
sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for
all of the CS42324’s in the system. If only one master clock source is needed, one solution is to place one
CS42324 in Master Mode, and slave all of the other devices to the one master.
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DS721A6