CS42324 Datasheet, PDF (59/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
6.17 DAC2x Volume Control: DAC1A (Address 14h) & DAC1B (Address 15h)
7
6
5
4
3
2
1
0
DAC2x_VOL7 DAC2x_VOL6 DAC2x_VOL5 DAC2x_VOL4 DAC2x_VOL3 DAC2x_VOL2 DAC2x_VOL1 DAC2x_VOL0
The level for each channel of DAC2 output can be adjusted in 0.5 dB increments as dictated by the DAC2
Soft and Zero Cross bits (DAC2_SOFT & DAC2_ZC) from 0 to -127.5 dB. Levels are decoded in unsigned,
as shown in the table below.
Binary Code
0000 0000
0000 0001
0000 0010
···
1111 1111
Volume Setting
0 dB
-0.5 dB
-1.0 dB
···
-127.5 dB
6.18 Interrupt Mode (Address 16h)
7
SP2_
CLKERR1
6
SP2_
CLKERR0
5
SP1_
CLKERR1
4
SP1_
CLKERR0
3
2
DAC_AMUTE1 DAC_AMUTE0
1
ADC_
OVFLx1
0
ADC_
OVFLx0
The Interrupt Mode register contains four two-bit codes which correspond to either an Interrupt Status bit or
group of bits as shown below. There are three ways to set the INT pin active in accordance with the interrupt
condition. In the Rising-edge Active Mode, the INT pin becomes active on the arrival of the interrupt condi-
tion. In the Falling-edge Active Mode, the INT pin becomes active on the removal of the interrupt condition.
In Level Active Mode, the INT pin remains active during the interrupt condition .
Interrupt Mode
SP2_CLKERR[1:0]
SP1_CLKERR[1:0]
DAC_AMUTE[1:0]
ADC_AVFLx[1:0]
Associated Interrupt Status Bit(s)
SP2_CLKERR
SP1_CLKERR
DAC2_AMUTEL, DAC2_AMUTER, DAC1_AMUTEL, DAC1_AMUTER
ADC_OVFLP, ADC_OVFLN
Bit Settings
00
01
10
11
Interrupt Mode Setting
Rising-edge Active
Falling-edge Active
Level Active
Reserved
6.19 Interrupt Mask (Address 17h)
7
DAC2_
AMUTELM
6
DAC2_
AMUTERM
5
DAC1_
AMUTELM
4
DAC1_
AMUTERM
3
SP2_
CLKERRM
2
SP1_
CLKERRM
1
ADC_
OVFLPM
0
ADC_
OVFLNM
These bits are mask bits for the corresponding bits in the “Interrupt Status (Address 18h) (Read Only)” reg-
ister on page 61.
Bit Settings
0
1
Bit in Interrupt Register
Not Masked
Masked
DS721A6
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