CS42324 Datasheet, PDF (35/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

4.4.3
CS42324
De-Emphasis Filter
The CS42324 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in Figure 17. The frequency response of the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 μs pre-emphasis
equalization as a means of noise reduction. De-emphasis is only available in Single-Speed Mode
Gain
dB
T1=50 µs
0dB
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 17. De-Emphasis Curve
4.4.4
4.4.5
Internal Digital Loopback
The CS42324 supports an internal digital loopback mode in which the ADC’s output data can be internally
routed to either of the DAC inputs. This mode may be activated by setting the DACx_LOOP_BACK bit in
“DAC1 Control (Address 0Bh)” on page 53 and “DAC2 Control (Address 0Ch)” on page 55. During this
mode, the ADC and DAC will need to operate at the same synchronous sample rate. When the
DACx_LOOP_BACK bit is set, the respective DACx_DIF[2:0] bits must be set to the same value as the
ADC_DIF[2:0] register.
During loop back mode, the ADC data will continue to be present on the SDOUT pin in the format selected
by the ADC_DIF[2:0] bits.
DAC Description
The CS42324 uses a switched current architecture followed by on chip current to voltage conversion and
continuous time low-pass filter. The digital interpolator response is shown in the “DAC Digital Filter Re-
sponse Plots” on page 67. The recommended external analog circuitry is shown in the “Typical Connec-
tion Diagrams” on page 26.
The CS42324 DAC does not include phase or amplitude compensation for an external filter. Therefore,
the DAC system phase and amplitude response will be dependent on the external analog circuitry.
DS721A6
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