CS42324 Datasheet, PDF (25/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
SWITCHING CHARACTERISTICS - SOFTWARE MODE - SPI FORMAT
Inputs: Logic ‘0’ = GND = GNDH = 0 V; Logic ‘1’ = VLC; C_L = 20 pF.
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling (Note 20)
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 21)
Rise Time of CCLK and CDIN (Note 22)
Fall Time of CCLK and CDIN (Note 22)
Transition Time from CCLK to CDOUT Valid (Note 23)
Time from CS rising to CDOUT High-Z
Symbol
Min
f_sclk
-
t_srs
500
t_spi
500
t_csh
1.0
t_css
20
t_scl
66
t_sch
66
t_dsu
40
t_dh
15
t_r2
-
t_f2
-
t_r2
-
t_f2
-
Max
6
-
-
-
-
-
-
-
-
100
100
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 20. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For F_SCK < 1 MHz.
23. CDOUT should not be sampled during this time.
RST
t _srs
CS
CCLK
CDIN
CDOUT
t _spi t _css
t _scl t _sch
t _r2
t _f2
t _csh
t _{dsu t dh}
H i-Im p e da n ce
t _scdov
t _scdov
t _cscdo
Figure 6. Software Mode Timing - SPI Mode
DS721A6
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