CS42324 Datasheet, PDF (37/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
4.4.7.3 Serial Interface Clock Changes
When changing the serial port clock ratio or sample rate, it is recommended that zero data (or near zero
data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking
change, the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at
the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it’s zero
data state.
4.4.8
Mute Control
The MUTECx pins become active during power-up initialization, reset, software/hardware muting, and
power-down mode (PDN=1). The MUTECx pins are intended to be used as control for an external mute
circuit in order to add off-chip mute capability.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. The MUTECx pins are active-low CMOS drivers.
4.5 Initialization
The initialization and Power-Down sequence flow chart is shown in Figure 19 on page 39. The CODEC en-
ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-
lators and software registers are reset. The internal voltage reference, multi-bit DACs and ADC, and on-chip
amplifiers are powered down.
4.5.1
Determining Hardware or Software Mode
The device will remain in the Power-Down state until the RST pin is brought high. If there is a pull-up on
SDOUT, or SDOUT is held high by any other means at the time RST pin is brought high, the device will
enter Hardware mode and begin powering up immediately. If no pull-up is present, or SDOUT is held low
by any other means at the time RST pin is brought high, the device will enter software mode.
4.5.2
Hardware Mode Start-Up
When the pull-up on SDOUT is present Hardware Mode is selected. Once hardware mode is selected,
the hardware mode configuration pins are used to set up the device and power-up will occur following the
HW startup path as shown in Figure 19 on page 39. The modes of configuration for this mode can be
found in Section 4.6.1 "Hardware Mode" on page 40. Because of the limited configuration abilities in Hard-
ware mode, many modes of operation are not available.
Only MCLK1 needs to be applied. Once the appropriate MCLK1 is valid and RST is high, the quiescent
voltage, VCMADC and VCMBUF, and the internal voltage references, FILT+ and VCM_ADC, will begin
powering up to normal operation. During this voltage reference ramp delay, both SDOUT and the
AOUTxA/AOUTxB outputs will be automatically muted. Once LRCKx is valid, MCLKx occurrences are
counted over one LRCKx period to determine the MCLKx/LRCKx frequency ratio and normal operation
begins.
It is recommended that RST be activated if the analog or digital supplies drop below the recommended
operating condition to prevent power-glitch-related issues.
DS721A6
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