CS42324 Datasheet, PDF (46/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

CS42324
6. REGISTER DESCRIPTION
All registers are read/write except where otherwise noted. See the following bit definition tables for bit assignment
information. The default state of each bit after release of reset is listed in the shaded row of each bit description
table. When writing to registers containing “Reserved” bits, all bits marked as “Reserved” must maintain their default
values.
6.1 Device I.D. and Revision Register (Address 00h) (Read Only)
7
DEVICE3
6
DEVICE2
5
DEVICE1
4
DEVICE0
3
REV3
2
REV2
1
REV1
0
REV0
6.1.1
Device I.D. (Read Only)
I.D. code for the CS42324.
DEVICE[3:0]
0110
CS42324
Device
6.1.2
Chip Revision (Read Only)
CS42324 revision level.
REV[3:0]
000
A1
001
B0
Revision Level
6.2 Mute Control (Address 01h)
7
Reserved
6
SYS_MCLK
5
DAC2_
MuteL
4
DAC2_
MuteR
3
DAC1_
MuteL
2
DAC1_
MuteR
1
ADC_
MuteL
0
ADC_
MuteR
6.2.1
System MCLK Source
This bit selects which MCLK pin provides the clock for internal state machines. It must always be set to
whichever clock is currently active.
SYS_MCLK
0
1
MCLK1
MCLK2
System MCLK source
6.2.2
Mute DAC2 Left-Channel
When set, this bit engages internal mute circuit on DAC2 output.
DAC2_MuteL
0
Un-muted
1
Muted
Mute status of DAC2 Left-channel
46
DS721A6