CS42324 Datasheet, PDF (29/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

4.1.2
CS42324
Synchronous / Asynchronous Mode
By default, the CS42324 operates in Synchronous Mode with both serial ports synchronous to MCLK1. In
this mode, the serial ports may operate at different synchronous rates as set by the SP1_SPEED and
SP2_SPEED bits, and MCLK2 does not need to be provided (the MCLK2 pin should be left unconnected
if not required).
If the SPx_MCLK (SPx = SP1 and/or SP2) bits in serial ports 1 and 2 are set differently, the CS42324 will
operate in Asynchronous Mode. The serial ports will operate asynchronously with Serial Port 1 clocked
from its SP1_MCLK selection and Serial Port 2 clocked from its SP2_MCLK selection. In this mode, the
serial ports may operate at different asynchronous rates.
In Hardware Mode MCLK1 is the master clock source for all internal circuits. Clock selection and asyn-
chronous operation are not available.
4.2
Serial Port Operation
Each CS42324 serial audio interface port operates as either a clock slave or master. They accept externally
generated clocks in slave mode (LRCKx and SCLKx pins are inputs, generated clocks shown in Figure 9
are disabled) and will generate synchronous clocks derived from an input master clock (MCLK1/MCLK2) in
master mode (LRCKx and SCLKx pins are outputs, generated clocks shown in Figure 9 are enabled).
LRCK1
pin
SCLK1
pin
SP1_M/S
Generated-LRCK1
SP1_M/S
Internal-LRCK1
To converters
Generated-SCLK1
Master
Mode
Clock
Generation
Figure 10
on page 30
Internal-SCLK1
To converters
LRCK2
pin
SCLK2
pin
SP2_M/S
Generated-LRCK2
SP2_M/S
Internal-LRCK2
To converters
Generated-SCLK2
Master
Mode
Clock
Generation
Figure 10
on page 30
Internal-SCLK2
To converters
Serial Port 1 (SP1)
Figure 9. Serial Port Topology
Serial Port 2 (SP2)
The LRCK, Fs, is the frequency at which audio samples for each channel are clocked into or out of the de-
vice. In slave mode, LRCK should be synchronously derived from the MCLK selected in SPx_MCLK regis-
ter.
The SCLK is the bit clock which is used to clock in the serial audio data stream. SCLK should adhere to the
timing requirements outlined in “Switching Characteristics - Serial Audio” on page 22.
The SP1_SPEED, SP2_SPEED, MCLK1 FREQ[1:0] and MCLK2 FREQ[1:0] Software Mode control bits or
the M1, M0, and MDIV hardware control pins, configure the device to generate the proper clocks in Master
Mode and receive the proper clocks in Slave Mode. In hardware mode, control pins M1 and M0 configure
the master/slave mode setting for the serial ports as well as the speed mode as shown in Table 5.
M0 (Pin 1)
0
0
1
1
M1 (Pin 2)
0
1
0
1
Serial Port Configuration
Clock Master, Single-Speed Mode
Clock Master, Double-Speed Mode
Reserved
Clock Slave, Auto-detect Speed Mode
Table 5. M1 and M0 Mode Pins in Hardware Mode
DS721A6
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