CS42324 Datasheet, PDF (33/71 Pages) Cirrus Logic – 10-In, 6-Out, 2 Vrms Audio CODEC

4.3 Analog-to-Digital Data Path
CS42324
4.3.1
ADC Analog Input Multiplexer
AINxA and AINxB are the analog inputs, internally biased to VCMADC. The CS42324 contains a stereo
5-to-1 analog input multiplexer which can select one of 5 possible stereo analog input sources and route
it to the ADC. Figure 16 shows the architecture of the input multiplexer.
AIN1A
AIN2A
AIN3A
AIN4A
AIN5A
MUX
Out to ADC
Channel A
AIN1B
AIN2B
AIN3B
AIN4B
AIN5B
AIN_SEL[2:0]
MUX
Out to ADC
Channel B
Figure 16. Analog Input Architecture
“Section 6.9 “ADC Control (Address 0Ah)” on page 52” outlines the bit settings necessary to control the in-
put multiplexer. By default, line level input 1 is selected.
4.3.2
ADC Description
The ADC analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for input signals which are
(n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Dia-
gram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of
capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided
since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
The ADC output data is in two’s complement binary format. For inputs above positive full-scale or below
negative full-scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to “ADC Analog Characteristics - Commercial (-CQZ)” on page 17 for
the specified offset level).
DS721A6
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