SAMA5D3_14 Datasheet, PDF (956/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

Without the alternative increment field the period of the clock would be limited to an integer number of nanoseconds,
resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250 MHz.
GMAC is configured to operate as PTP slave. The timer register increments as normal but the timer value is copied to the
sync strobe register.
There are six additional 62-bit registers that capture the time at which PTP event frames are transmitted and received.
An interrupt is issued when these registers are updated.
37.5.16 MAC 802.3 Pause Frame Support
Note: See Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of MAC 802.3 pause
operation.
The following table shows the start of a MAC 802.3 pause frame.
Table 37-13. Start of an 802.3 Pause Frame
Address
Destination
Source
Type
(MAC Control Frame)
0x0180C2000001
6 bytes
0x8808
Pause
Opcode
Time
0x0001
2 bytes
The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and hardware
generated pause frame transmission.
37.5.16.1 802.3 Pause Frame Reception
Bit 13 of the Network Configuration Register is the pause enable control for reception. If this bit is set, transmission will
pause if a non zero pause quantum frame is received.
If a valid pause frame is received then the Pause Time Register is updated with the new frame's pause time, regardless
of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status Register) is
triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt
Mask Register). Pause frames received with non zero quantum are indicated through the interrupt bit 12 of the Interrupt
Status Register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status Register.
Once the Pause Time Register is loaded and the frame currently being transmitted has been sent, no new frames are
transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of transmission,
only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex there will be
no transmission pause, but the pause frame received interrupt will still be triggered. A valid pause frame is defined as
having a destination address that matches either the address stored in Specific Address Register 1 or if it matches the
reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause
opcode of 0x0001.
Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded.
802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will also be
discarded. Valid pause frames received will increment the pause frames received statistic register.
The pause time register decrements every 512 bit times once transmission has stopped. For test purposes, the retry test
bit can be set (bit 12 in the Network Configuration Register) which causes the Pause Time Register to decrement every
GTXCK cycle once transmission has stopped.
The interrupt (bit 13 in the Interrupt Status Register) is asserted whenever the Pause Time Register decrements to zero
(assuming it has been enabled by bit 13 in the Interrupt Mask Register). This interrupt is also set when a zero quantum
pause frame is received.
37.5.16.2 802.3 Pause Frame Transmission
Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control
Register. If either bit 11 or bit 12 of the Network Control Register is written with logic 1, an 802.3 pause frame will be
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
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