SAMA5D3_14 Datasheet, PDF (1186/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

39.14.8 HSMCI Completion Signal Timeout Register
Name:
HSMCI_CSTOR
Address: 0xF000001C (0), 0xF800001C (1), 0xF800401C (2)
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
–
–
–
–
7
6
5
4
3
2
1
0
–
CSTOMUL
CSTOCYC
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protection Mode Register” on page 1201.
• CSTOCYC: Completion Signal Timeout Cycle Number
This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer
and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA
ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the completion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
Value
0
1
2
3
4
5
6
7
Name
1
16
128
256
1024
4096
65536
1048576
Description
CSTOCYC x 1
CSTOCYC x 16
CSTOCYC x 128
CSTOCYC x 256
CSTOCYC x 1024
CSTOCYC x 4096
CSTOCYC x 65536
CSTOCYC x 1048576
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag (CSTOE) in
the HSMCI Status Register (HSMCI_SR) rises.
SAMA5D3 Series [DATASHEET] 1186
11121D–ATARM–03-Apr-14