SAMA5D3_14 Datasheet, PDF (700/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

33.7.78 High End Overlay Layer Channel Status Register
Name:
LCDC_HEOCHSR
Address: 0xF0030348
Access:
Read-only
Reset:
0x00000000
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
–
–
–
–
–
7
6
5
4
3
–
–
–
–
–
26
–
18
–
10
–
2
A2QSR
25
–
17
–
9
–
1
UPDATESR
• CHSR: Channel Status Register
When set to one this field disables the layer at the end of the current frame.
• UPDATESR: Update Overlay Attributes In Progress
When set to one this bit indicates that the overlay attributes will be updated on the next frame.
• A2QSR: Add To Queue Pending Register
When set to one this bit indicates that the head pointer is still pending.
24
–
16
–
8
–
0
CHSR
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
700