SAMA5D3_14 Datasheet, PDF (1675/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

52. Advanced Encryption Standard (AES)
52.1 Description
The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing
Standard) Publication 197 specification.
The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC,
OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation. It is compatible with all
these modes via Peripheral DMA Controller channels, minimizing processor intervention for large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit registers (AES_KEYWRx) which are all write-only.
The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit registers (AES_IDATARx
and AES_IVRx) which are all write-only.
As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be
started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit output data registers
(AES_ODATARx) or through the DMA channels.
52.2
Embedded Characteristics
 Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
 128-bit/192-bit/256-bit Cryptographic Key
 12/14/16 Clock Cycles Encryption/Decryption Processing Time with a 128-bit/192-bit/256-bit Cryptographic Key
 Double Input Buffer Optimizes Runtime
 Support of the Five Standard Modes of Operation Specified in the NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
 Electronic Code Book (ECB)
 Cipher Block Chaining (CBC) including CBC-MAC
 Cipher Feedback (CFB)
 Output Feedback (OFB)
 Counter (CTR)
 8-, 16-, 32-, 64- and 128-bit Data Sizes Possible in CFB Mode
 Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation
 Connection to DMA Optimizes Data Transfers for all Operating Modes
52.3 Product Dependencies
52.3.1 Power Management
The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure
the PMC to enable the AES clock.
52.3.2 Interrupt
The AES interface has an interrupt line connected to the Interrupt Controller.
Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES.
Table 52-1. Peripheral IDs
Instance
ID
AES
43
SAMA5D3 Series [DATASHEET] 1675
11121D–ATARM–03-Apr-14