SAMA5D3_14 Datasheet, PDF (1499/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

48. Timer Counter (TC)
48.1
Description
The Timer Counter (TC) includes 6 identical 32-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including frequency
measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which
can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate
processor interrupts.
The Timer Counter block has two global registers which act upon all TC channels:
 Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction
 Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be chained
Table 48-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2.
Table 48-1. Timer Counter Clock Assignment
Name
Definition
TIMER_CLOCK1
div2
TIMER_CLOCK2
div8
TIMER_CLOCK3
div32
TIMER_CLOCK4
div128
TIMER_CLOCK5⁽¹⁾
slow_clock
Note: 1. When Slow Clock is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register),
TIMER_CLOCK5 input is equivalent to Peripheral Clock.
48.2
Embedded Characteristics
 Provides 6 32-bit Timer Counter channels
 Wide range of functions including:
 Frequency measurement
 Event counting
 Interval measurement
 Pulse generation
 Delay timing
 Pulse Width Modulation
 Up/down capabilities
 2-bit gray up/down count for stepper motor
 Each channel is user-configurable and contains:
 Three external clock inputs
 Five Internal clock inputs
 Two multi-purpose input/output signals acting as trigger event
 Internal interrupt signal
 Two global registers that act on all TC channels
 Register Write Protection
SAMA5D3 Series [DATASHEET] 1499
11121D–ATARM–03-Apr-14