SAMA5D3_14 Datasheet, PDF (512/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

32.3
DMA Controller Peripheral Connections
The DMA Controller handles the transfer between peripherals and memory and receives triggers from the peripherals
listed in tables that follow.
For each listed DMA Channel Number, the SIF and/or DIF bitfields in the DMAC_CTRLBx register must be programmed
with a value compatible to the MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section
of the product datasheet. See Section 32.8.17 ”DMAC Channel x [x = 0..7] Control B Register” (where x is the DMA
Channel Number).
Depending on transfer descriptor location, the DSCR_IF bitfield must be programmed with a value compatible to the
MATRIX “Master to Slave Access” definition provided in the “Bus Matrix (MATRIX)” section of the product datasheet. See
Section 32.8.15 ”DMAC Channel x [x = 0..7] Descriptor Address Register” (where x is the DMA Channel Number).
32.3.1 DMA Controller 0
The DMA Controller 0 handles the transfer between peripherals and memory and receives triggers from the
peripherals connected on APB0 (see Table 32-1).
Table 32-1. DMA Channels Definition (DMAC0)
Instance name Channel T/R
Interface number
HSMCI0
Receive/transmit
0
SPI0
Transmit
1
SPI0
Receive
2
USART0
Transmit
3
USART0
Receive
4
USART1
Transmit
5
USART1
Receive
6
TWI0
Transmit
7
TWI0
Receive
8
TWI1
Transmit
9
TWI1
Receive
10
UART0
Transmit
11
UART0
Receive
12
SSC0
Transmit
13
SSC0
Receive
14
SMD
Transmit
15
SMD
Receive
16
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
512