SAMA5D3_14 Datasheet, PDF (1563/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

49.7.1 PWM Clock Register
Name:
PWM_CLK
Address: 0xF002C000
Access:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
PREB
23
22
21
20
19
18
17
16
DIVB
15
14
13
12
11
10
9
8
–
–
–
–
PREA
7
6
5
4
3
2
1
0
DIVA
This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the “PWM Write Protection Status Register” .
• DIVA, DIVB: CLKA, CLKB Divide Factor
DIVA, DIVB
0
1
2–255
CLKA, CLKB
CLKA, CLKB clock is turned off
CLKA, CLKB clock is clock selected by PREA, PREB
CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
• PREA, PREB: CLKA, CLKB Source Clock Selection
PREA, PREB
Divider Input Clock
0
0
0
0
MCK
0
0
0
1
MCK/2
0
0
1
0
MCK/4
0
0
1
1
MCK/8
0
1
0
0
MCK/16
0
1
0
1
MCK/32
0
1
1
0
MCK/64
0
1
1
1
MCK/128
1
0
0
0
MCK/256
1
0
0
1
MCK/512
1
0
1
0
MCK/1024
Other
Reserved
SAMA5D3 Series [DATASHEET] 1563
11121D–ATARM–03-Apr-14