SAMA5D3_14 Datasheet, PDF (943/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

If any errors occur on the AHB while reading the transmit frame, the fetching of packet data from AHB memory is halted.
The MAC transmitter will continue to fetch packet data, thereby emptying the packet buffer and allowing any good non-
errored frames to be transmitted successfully. Once these have been fully transmitted, the status/statistics for the errored
frame will be updated and software will be informed via an interrupt that an AHB error occurred. This way, the error is
reported in the correct packet order.
The transmit packet buffer will only attempt to read more frame data from the AHB when space is available in the packet
buffer memory. If space is not available it must wait until the a packet fetched by the MAC completes transmission and is
subsequently removed from the packet buffer memory. Note that if full store and forward mode is active and if a single
frame is fetched that is too large for the packet buffer memory, the frame is flushed and the DMA halted with an error
status. This is because a complete frame must be written into the packet buffer before transmission can begin, and
therefore the minimum packet buffer memory size should be chosen to satisfy the maximum frame to be transmitted in
the application.
In full store and forward mode, once the complete transmit frame is written into the packet buffer memory, a trigger is
sent across to the MAC transmitter, which will then begin reading the frame from the packet buffer memory. Since the
whole frame is present and stable in the packet buffer memory an underflow of the transmitter is not possible. The frame
is kept in the packet buffer until notification is received from the MAC that the frame data has either been successfully
transmitted or can no longer be retransmitted (too many retries in half duplex mode). When this notification is received
the frame is flushed from memory to make room for a new frame to be fetched from AHB system memory.
In partial store and forward mode, a trigger is sent across to the MAC transmitter as soon as sufficient packet data is
available, which will then begin fetching the frame from the packet buffer memory. If, after this point, the MAC transmitter
is able to fetch data from the packet buffer faster than the AHB DMA can fill it, an underflow of the transmitter is possible.
In this case, the transmission is terminated early, and the packet buffer is completely flushed. Transmission can only be
restarted by writing to the transmit START bit.
In half duplex mode, the frame is kept in the packet buffer until notification is received from the MAC that the frame data
has either been successfully transmitted or can no longer be retransmitted (too many retries in half duplex mode). When
this notification is received the frame is flushed from memory to make room for a new frame to be fetched from AHB
system memory.
In full duplex mode, the frame is removed from the packet buffer on the fly.
Other than underflow, the only MAC related errors that can occur are due to collisions during half duplex transmissions.
When a collision occurs the frame still exists in the packet buffer memory so can be retried directly from there. Only once
the MAC transmitter has failed to transmit after sixteen attempts is the frame finally flushed from the packet buffer.
37.5.3.8 Receive Packet Buffer
The receive packet buffer stores frames from the MAC receiver along with their status and statistics. Frames with errors
are flushed from the packet buffer memory, while good frames are pushed onto the DMA AHB interface.
The receiver packet buffer monitors FIFO from the MAC receiver and translates the FIFO pushes into packet buffer
writes. At the end of the received frame the status and statistics are buffered so that the information can be used when
the frame is read out. When programmed in full store and forward mode, if the frame has an error the frame data is
immediately flushed from the packet buffer memory allowing subsequent frames to utilise the freed up space. The status
and statistics for bad frames are still used to update the GMAC registers.
To accommodate the status and statistics associated with each frame, three words per packet (or two if configured in 64-
bit datapath mode) are reserved at the end of the packet data. If the packet is bad and requires to be dropped, the status
and statistics are the only information held on that packet.
The receiver packet buffer will also detect a full condition so that an overflow condition can be detected. If this occurs,
subsequent packets are dropped and an RX overflow interrupt is raised.
For full store and forward, the DMA only begins packet fetches once the status and statistics for a frame are available. If
the frame has a bad status due to a frame error, the status and statistics are passed onto the GMAC registers. If the
frame has a good status, the information is used to read the frame from the packet buffer memory and burst onto the
AHB using the DMA buffer management protocol. Once the last frame data has been transferred to the FIFO, the status
and statistics are updated to the GMAC registers.
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
943