SAMA5D3_14 Datasheet, PDF (906/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

• ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enabled
0: ISO CRC error/number of Transaction Error Interrupt is masked.
1: ISO CRC error/number of Transaction Error Interrupt is enabled.
• ERR_FLUSH: Bank Flush Error Interrupt Enabled
0: Bank Flush Error Interrupt is masked.
1: Bank Flush Error Interrupt is enabled.
• BUSY_BANK: Busy Bank Interrupt Enabled
0: BUSY_BANK Interrupt is masked.
1: BUSY_BANK Interrupt is enabled.
For OUT endpoints: An interrupt is sent when all banks are busy.
For IN endpoints: An interrupt is sent when all banks are free.
• SHRT_PCKT: Short Packet Interrupt Enabled
For OUT endpoints: send an Interrupt when a Short Packet has been received.
0: Short Packet Interrupt is masked.
1: Short Packet Interrupt is enabled.
For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling an end of isochro-
nous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register
AUTO_VALID bits are also set.
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
906