SAMA5D3_14 Datasheet, PDF (788/1840 Pages) ATMEL Corporation – ARM-based Embedded MPU

33.7.158Post Processing Layer Channel Disable Register
Name:
LCDC_PPCHDR
Address: 0xF0030544
Access:
Write-only
Reset:
0x00000000
31
30
29
28
27
26
–
–
–
–
–
–
23
22
21
20
19
18
–
–
–
–
–
–
15
14
13
12
11
10
–
–
–
–
–
–
7
6
5
4
3
2
–
–
–
–
–
–
• CHDIS: Channel Disable Register
When set to one this field disables the layer at the end of the current frame.
• CHRST: Channel Reset Register
When set to one this field disables the layer at the end of the current frame.
25
24
–
–
17
16
–
–
9
8
–
CHRST
1
0
–
CHDIS
SAMA5D3 Series [DATASHEET]
11121D–ATARM–03-Apr-14
788