SAMA5D43_14 Datasheet, PDF (937/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

35.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint)
Name:
UDPHS_EPTSETSTAx [x=0..15] (ISOENDPT)
Address: 0xFC02C114 [0], 0xFC02C134 [1], 0xFC02C154 [2], 0xFC02C174 [3], 0xFC02C194 [4], 0xFC02C1B4 [5],
0xFC02C1D4 [6], 0xFC02C1F4 [7], 0xFC02C214 [8], 0xFC02C234 [9], 0xFC02C254 [10], 0xFC02C274 [11],
0xFC02C294 [12], 0xFC02C2B4 [13], 0xFC02C2D4 [14], 0xFC02C2F4 [15]
Access:
Write-only
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
TXRDY_TRER
–
RXRDY_TXKL
–
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
–
This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register” on page 920.
For additional information, see “UDPHS Endpoint Status Register (Isochronous Endpoint)” on page 946.
• RXRDY_TXKL: KILL Bank Set (for IN Endpoint)
0: No effect.
1: Kill the last written bank.
• TXRDY_TRER: TX Packet Ready Set
0: No effect.
1: Set this bit after a packet has been written into the endpoint FIFO for IN data transfers
– This flag is used to generate a Data IN transaction (device to host).
– Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared.
– Transfer to the FIFO is done by writing in the “Buffer Address” register.
– Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting
TXRDY_TRER to one.
– UDPHS bus transactions can start.
– TXCOMP is set once the data payload has been sent.
– Data should be written into the endpoint FIFO only after this bit has been cleared.
– Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
937