SAMA5D43_14 Datasheet, PDF (595/1776 Pages) ATMEL Corporation – Atmel | SMART ARM-based Embedded MPU

31.7 XDMAC Maintenance Software Operations
31.7.1 Disabling a Channel
A disable channel request occurs when a write operation is performed in the XDMAC_GD register. If the channel is
source peripheral synchronized (bit XDMAC_CCx.TYPE is set and bit XDMAC_CCx.DSYNC is cleared), then
pending bytes (bytes located in the FIFO) are written to memory and bit XDMAC_CISx.DIS is set. If the channel is
not source peripheral synchronized, the current channel transaction (read or write) is terminated and
XDMAC_CISx.DIS is set. XDMAC_GS.STx is cleared by hardware when the current transfer is completed. The
channel is no longer active and can be reused.
31.7.2 Suspending a Channel
A read request suspend command is issued by writing to the XDMAC_GRS register. A write request suspend
command is issued by writing to the XDMAC_GWS register. A read write suspend channel is issued by writing to
the XDMAC_GRWS register. These commands have an immediate effect on the scheduling of both read and write
transactions. If a transaction is already in progress, it is terminated normally. The channel is not disabled. The
FIFO content is preserved. The scheduling mechanism can resume normally, clearing the bit in the same
registers. Pending bytes located in the FIFO are not written out to memory. The write suspend command does not
affect read request operations, i.e., read operations can still occur until the FIFO is full.
31.7.3 Flushing a Channel
A FIFO flush command is issued writing to the XDMAC_SWF register. The content of the FIFO is written to
memory. XDMAC_CISx.FIS (End of Flush Interrupt Status bit) is set when the last byte is successfully transferred
to memory. The channel is not disabled. The flush operation is not blocking, meaning that read operation can be
scheduled during the flush write operation. The flush operation is only relevant for peripheral to memory transfer
where pending peripheral bytes are buffered into the channel FIFO.
31.7.4 Maintenance Operation Priority
31.7.4.1 Disable Operation Priority
 When a disable request occurs on a suspended channel, the XDMAC_GWS.WSx (Channel x Write
Suspend bit) is cleared. If the transfer is source peripheral synchronized, the pending bytes are drained to
memory. The bit XDMAC_CISx.DIS is set.
 When a disable request follows a flush request, if the flush last transaction is not yet scheduled, the flush
request is discarded and the disable procedure is applied. The bit XDMAC_CISx.FIS is not set. Bit
XDMAC_CISx.DIS will be set when the disable request is completed. If the flush request transaction is
already scheduled, the XDMAC_CISx.FIS will be set. XDMAC_CISx.DIS will also be set when the disable
request is completed.
31.7.4.2 Flush Operation Priority
 When a flush request occurs on a suspended channel, if there are pending bytes in the FIFO, they are
written out to memory, XDMAC_CISx.FIS is set. If the FIFO is empty, XDMAC_CISx.FIS is also set.
 If the flush operation is performed after a disable request, the flush command is ignored. XDMAC_CISx.FIS
is not set.
31.7.4.3 Suspend Operation Priority
If the suspend operation is performed after a disable request, the write suspend operation is ignored.
SAMA5D4 Series [DATASHEET]
Atmel-11238A-ATARM-SAMA5D4-Datasheet_30-Sep-14
595